1. Field of the Invention
This invention relates to semiconductor fabrication technologies, and more particularly, to a method of fabricating a coronary-type capacitor to serve as a data storage element in a semiconductor memory device, such as a DRAM (dynamic random-access memory) device.
2. Description of Related Art:
A single memory cell of a DRAM device typically includes a transfer field effect transistor (TFET) and a data storage capacitor. Whether a DRAM cell stores a binary value of 1 or 0 is dependent on whether the capacitor element therein is fully charged or discharged. Fundamentally, the charge retaining capability of the capacitor is proportional to its capacitance, and the capacitance is proportional to the surface area of the electrodes of the capacitor.
FIG. 1 is a schematic diagram showing the equivalent circuit structure of one memory cell of a typical DRAM device, which includes a MOS (metal-oxide semiconductor) transistor 11 serving as the TFET and a data storage capacitor 12. The MOS transistor 11 is formed in such a manner that its gate is connected to a word line WL, its source is connected to a bit line BL, and its drain is connected via the capacitor 12 to the ground. Whether the memory cell stores a binary data bit 0 or 1 is dependent on whether the capacitor 12 is fully charged or discharged. For example, the capacitor 12 retains a high voltage when fully charged. This high voltage represents storage of a first binary value, for example, 1, in the capacitor 12. In contrast, the capacitor 12 retains a null voltage when fully discharged. This null voltage represents storage of a second binary value, for example, 0, in the capacitor. Moreover, access to the capacitor 12, whether read or write, is controlled by the MOS transistor 11 whose ON/OFF state is controlled by the voltage state on the wordline WL.
In the fabrication of DRAMs with less than 1 MB (megabit) in capacity, it is a customary practice to utilize a two-dimensional capacitor called a planar-type capacitor as the data storage capacitor for each memory cell. Since the planar-type capacitor takes up quite a large layout area on the substrate, it is poorly suited for use in very large integration DRAMs. For 4 MB or higher DRAMs, a three-dimensional capacitor, such as a stacked-type or a trench-type capacitor, is utilized instead.
Compared to the planar-type capacitor, both the stacked-type capacitor and the trench-type capacitor can provide a relatively larger capacitance that allows the DRAM device to be further downsized while still allowing a good charge (data) retaining capability. However, when it comes to DRAMs of 64 MB or higher, both the stacked-type capacitor and the trench-type capacitor become inadequate.
One solution to the foregoing problem is to utilize the so-called fin-type capacitor. This type of capacitor has a very large capacitance due to the formation of a stacked structure with a plurality of horizontally extended conductive layers that are shaped like a fin to serve as the electrode of the capacitor.
Another solution is to utilize the so-called cylindrical-type capacitor. This type of capacitor also has a very large capacitance due to the formation of a vertically extended, cylindrically shaped electrode structure. This structure helps increase the surface area of the electrode, and thereby increase the capacitance of the capacitor.
A conventional method for fabricating a stacked-type capacitor for a DRAM device is illustratively depicted in the following with reference to FIGS. 2A-2D.
FIG. 2A shows a stacked-type capacitor constructed on a semiconductor substrate 20, which is already formed with a plurality of field oxide layers 21 at predefined locations to delineate the active regions on the substrate 20. Then, a tungsten silicide layer 22 and a first polysilicon layer 23 are successively formed to constitute a gate structure. A spacer structure 25 is then formed on the sidewall of the gate structure. Further, a pair of source/drain regions 24a, 24b are formed in the substrate 20. The gate structure (22, 23) and the source/drain regions 24a, 24b in combination constitute one MOS transistor for one memory cell of the DRAM device.
Referring next to FIG. 2B, in the subsequent step, a first insulating layer 26 is formed to cover the gate structure, formed by tungsten silicide layer 22 and first polysilicon layer 23, and the source/drain regions 24a, 24b. The first insulating layer 26 is preferably formed from TEOS (tetra-ethyl-ortho-silicate) through an LPCVD (low-pressure chemical-vapor deposition) process to a thickness of about 1,500 .ANG. (angstrom). Next, a microlithographic and etching process is performed on the first insulating layer 26 so as to define and form a contact window in the first insulating layer 26. The contact window exposes the source/drain region 24a. Subsequently, a second polysilicon layer 27 is formed over the contact window to a predefined extent. After this, a layer of tungsten silicide 28 is formed over the second polysilicon layer 27. The second polysilicon layer 27 is further doped with an impurity element so as to increase the conductivity of the second polysilicon layer 27. A second insulating layer 29 is then formed over the entire top surface of the wafer through, for example, an APCVD (atmospheric-pressure chemical-vapor deposition) process to a thickness of about 1,500 .ANG.. The second insulating layer 29 covers all the exposed surfaces of the first insulating layer 26, the second polysilicon layer 27, and the tungsten silicide layer 28. After this, a layer of borophosphosilicate glass (BPSG) 30 is formed through a reflow process at a temperature of about 850.degree. C. and an etch-back process to a thickness of about 4,500 .ANG.. Subsequently, a hard mask layer 31 is formed by, for example, first depositing a layer of silicon nitride (SiN) over the BPSG layer 30 to a thickness of about 500 .ANG., and then performing a microlithographic and etching process on the SiN layer to remove selected portions of the SiN layer.
Referring next to FIG. 2C, in the subsequent step, an etching process is performed on the wafer, with the hard mask layer 31 serving as an etching protection layer. This etching process opens a contact window 32 to expose the source/drain region 24b. Next, a doped polysilicon layer 34 is formed to a thickness of about 1,000 .ANG. over the top surface of the hard mask layer 31, the sidewall of the contact window 32, and the exposed surface of the source/drain region 24b.
Referring further to FIG. 2D, in the subsequent step, a dielectric layer 36 is deposited over the doped polysilicon layer 34. The dielectric layer 36 can be either a three-layer ONO (silicon dioxide, silicon nitride, and silicon dioxide) structure, a two-layer NO (silicon dioxide and silicon nitride) structure, or a layer of Ta.sub.2 O.sub.5. After this, a fourth doped polysilicon layer 37 is formed over the dielectric layer 36, which serves as one electrode for one memory cell of the DRAM device.
The foregoing stacked-type capacitor is presently widely utilized in many DRAM products as the data storage element. It is characterized by the formation of a morphology particular to the surface of the electrode structure that allows a relatively large surface area, which in turn allows the resultant capacitor to have a large capacitance.
Despite all of the above-mentioned types of capacitors, the semiconductor industry nevertheless exists a need for newer electrode structures that can help increase the capacitance of the data storage capacitor in DRAM devices, so that the DRAM devices can be further downsized for higher integration while nonetheless retaining reliable data storage capability.